搜索资源列表
fax
- 基于GSM,FAX Modem2.0的无线传真，操作系统为linux,cpu 为mips-Based on GSM, FAX Modem2.0 of the Wi-Fi, operating system, linux, cpu for mips
mipsfinal
- 用vhdl设计的一个mips小型cpu，不带流水，有r类，i类，j类指令都有~·-Using vhdl design a mips small cpu, with no running water, there are r class, i type, j class instruction have ~*
multi_cpu
- 多周期CPU，mips指令集，实现了部分指令，包含测试程序，verilog-Multi-cycle CPU
cpu_1
- mips单周期cpu设计，实现MIPS中的11条指令，在设计的cpu中运行快速排序程序进行验证。-mips one cycle cpu design,run quick sort promgram for test.
MIPS_CPU
- MIPS结构的CPU，采用VHDL编码，附带验证程序，能够跑题hash算法，流水灯，求π程序-MIPS structure of the CPU, using VHDL coding, with the verification process, to get off track and hash algorithms, water lights, find π procedures
mipsr4000User_Manual
- mips4000使用手册,非常经典的一款CPU,是初学mips的好东西-mips4000 manual, very classic a CPU, is a good thing beginners mips
Windows_CE_OAL
- Windows CE微软针对嵌入式领域推出的一款全新的操作系统。之所以说它是一款全新的操作系统，是因为尽管Windows CE的UI非常接近其它的桌面版Windows操作系统，但是它的内核完全是重新写的，并不是任何一款桌面版Windows的精简版本。 Windows CE是一种支持多种CPU架构的操作系统，其中包括ARM、x86、MIPS和SHx，极大地减轻了OEM开发过程中移植操作系统的工作量-The field of Microsoft Windows CE for embedded in
MIPS32
- MIPS32指令集兼容的CPU模拟器设计 健词：MIPs处理器；模拟器；高速缓存；分支预-of CPU Simulator Compatible with MIPS32 Instruction Set A design scheme of a CPu simulator which is compatjble with MIPS32 instruction set is presented．
A-RISC-Design
- RISC设计：MIPS指令集控制器核，详细介绍一款32位risc-cpu。-A RISC Design:Synthesis of the MIPS Processor Core
MIPS_CPU_OR2000
- MIPS架构的开发的CPU软核OR2000 verilog实现，MIPS体系结构cpu设计入门参考-The development of the MIPS architecture CPU soft core OR2000
Vxworksspeech
- VxWorks是一种嵌入式的实时操作系统，所谓嵌入式系统就是用户自己开发设计板子，板子上通常有一颗CPU，VxWorks支持32位的CPU，包括Intel公司的x86、Motorola公司的68k和PowerPC、MIPS、ARM、Intel公司的i960、Hitachi公司的SH-VxWorks is a real-time embedded operating system, the so-called embedded systems development and design is t
lec05_bo_lenh_mips_3374_1132
- continue Mips tool ilustrate cpu
Project1
- Calculate CPI,CPU time and MIPS of a sequence. -Calculate CPI,CPU time and MIPS of a sequence.
singlePcyclePMIPS2
- 多周期MIPS实现的CPU设计方案，包括源码-MIPS multi-cycle
MIPS_Pipelined_CPU
- MIPS Pipelined CPU written on VHDL with commands, 5 stage pipeline
ALU
- 11条指令MIPS指令系统CPU中的ALU设计-11 instruction in the MIPS instruction ALU design in the system CPU
cycle_code
- verilog实现了MIPS多周期（5周期）的CPU-verilog MIPS 5 cylce
yuanma
- MIPS指令源代码，用于CPU设计，计算机组成原理课设所需要的源代码下载-MIPS instruction source code for the CPU design, computer composition principle lesson to set the source code download
mips_single
- 這是以verilog所撰寫的MIPS single CPU文件檔。可完成簡單的加減運算。 -This is the verilog are written in MIPS single CPU document file. To be completed by the simple addition and subtraction.
MIPSTIXI
- MIPS体系结构详解,讲解CPU的MMU以及Cache等内容,有助于对CPU入门学习-Detailed MIPS architecture, explain the CPU s MMU and Cache content helps to learn the CPU entry